What is CMSIS?

CMSIS is an acronym for Cortex Microcontroller Software Interface Standard.


CMSIS is an abstract layer that supports developers and vendors in creating reusable software components for ARM Cortex-M based systems. This layer is useable for Cortex-M0,M0+, M1 M3/M4 layers as well.


A brief glance into Cortex-M0,M0+, M1, M3 and M4 architectures:

• Cortex-M0: The ARM Cortex™-M0 processor is the smallest ARM processor available. The exceptionally small silicon area, low power and minimal code footprint of the processor enables developers to achieve 32-bit performance at an 8-bit price point.
• Supports 3-stage pipeline, thumb2, hardware-single-cycle (32x32) multiply hardware.
• Supports 1 NMI and 32 physical interrupts.
• Has only 56 instructions and has 'C-friendly' architecture.  

• Cortex-M0+: The ARM Cortex™-M0+ processor is an adaption of Cortex-M0 but with more improved performance and reduced energy footprint.
• Supports 2-stage pipeline, thumb2, hardware-single-cycle(32x32) multiply hardware.

• Cortex-M1: The ARM Cortex™-M1 processor is the first ARM processor designed specifically for implementation in FPGAs. 
• Supports 3-stage pipeline, thumb2 and big & little endian configuration. 

• Cortex-M3: The ARM Cortex™-M3 processor is the industry-leading 32-bit processor for highly deterministic real-time applications, specifically developed to enable partners to develop high-performance low-cost platforms for a broad range of devices including microcontrollers, automotive body systems, industrial control systems and wireless networking and sensors.
• The Cortex-M3 NVIC is highly configurable at design time to deliver up to 240 system interrupts with individual priorities, dynamic reprioritization and integrated system clock.
• Supports 1 NMI  and 240 physical interrupts with 8 to 256 level priorities.
• Supports hardware divide, single cycle-multiply and saturated math support.

•  Cortex-M4: The ARM Cortex™-M4 processor  is the latest embedded processor by ARM specifically developed to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities.

• Supports 3-stage pipeline with branch prediction and thumb2.
• Supports hardware-divide, 8/16 bit SIMD arithmetic.
• Supports single precision floating point unit.
• Supports Memory protection unit and deterministic operations.

 

Continuing further on CMSIS:

In order to reduce cost and software complexity and the fact that there are too rapid changes on the technology front, CMSIS provides a uniform hardware abstraction layer that governs the way we write  and debug software by ensuring software re-useability.

CMSIS structure consists of three layers:

1. Core peripheral Access Layer (CPAL)
2. Middleware Access Layer (MAL)
3. Device peripheral Access Layer (DPAL)

CMSIS functional Flow (Courtesy: https://www.doulos.com)

Functionality of each CMSIS layer:

Core Peripheral Access Layer: This layer is provided by ARM. The lowest level defines addresses, and access methods for common components and functionality that exists in every Cortex-M system. Access to core registers, NVIC, debug subsystem is provided by this layer.

Middleware Access Layer:This layer is defined by ARM, but is also adapted by silicon vendors for their respective devices.The Middleware Access Layer defines a common API for accessing peripherals.

  

Device Peripheral Access Layer:This layer is provided by the silicon vendor and contains the hardware register addresses and other device specific  access functions.