Know your chip on NUC140 EVM board

The highlights of the NUC140 chip on the learning board:

1. Maximum supported CPU frequency via PLL is 50Mhz.
2. Maximum supported CPU frequency via external crystal is 24Mhz
3. Has inbuilt RTC with crystal of value 32.768Khz soldered to the learning board.
4. It can also run out of internal oscillator value of 22.1184Mhz.
5. Know your NUC140 series on your Learning board (EVM) of Nuvoton. The CPU name is NUC140VE3AN*.

• NUC series in Nuvoton means it is a 32 bit microcontroller series.
• 1 in letter 140 means: It has 1 core only i.e. Cortex M0.
• 4 in letter 140 means: It belongs to the connectivity range.
• 0 in letter 140 currently does not hold any specific meaning.
• V in VE3AN means: LQFP100 package
• E in VE3AN means: 128KB APROM size
• 3 in VE3AN means: 16KB RAM size
• A in VE3AN is reserved for future feature additions/revisions
• N in VE3AN means: temperature range supported by chip is: -40C to +85C. 
• The chip is based on ARM v6-M architecture.

8. It has 128KB for Program FLASH, 16KB for SRAM,  4KB Data flash and 4KB of LDROM (bootloader) and 76 IOs.
9. The page erase size of the dataflash is 512 bytes.
10. It has an inbuilt 12 bit resolution SAR ADC.
11. It has an inbuilt temperature sensor with an accuracy of +/-1 degree.
12. For the automotive line, it has support for BOSCH CAN 2.0 A/B and LIN support.
13. It has 4-32bit timers, 3-UARTs, 4-SPI channels, 2-I2C channels, 1-2.0v full-speed USB.
14.It has 8-16bit PWM channels and 2-Analog Comparators and 1-12S/AC97.

*There are other versions of NUC140 also available as per this ordering mechanism:

NUC140 Hardware chip ordering options as provided by Nuvoton

The nested vectored interrupt controller (NVIC) supports tail-chaining and late-arrival to assist in developing true real time embedded applications.

• Tail chaining is a method where the ISR, when it has executed and is about to return back to the main method and is in the process of restoring the state of the registers, if during that period another ISR occurs then the overhead of restoring and saving of the state is reduced by directly allowing the NVIC to jump from one ISR to the other and there by saving time in ISR overheads.
• Late-arrival is a method where when one ISR is about to get executed (but not started), if another higher priority ISR fires then the NVIC allows the higher priority ISR to execute first there by eliminating any delay to allow the most highest priority ISR to execute.

The CLOCK CONTROLLER of this chip:

It is very important to understand the variety of clock options provided by the controller which clocks the various peripherals. It is hence important to understand the clock options to calculate the clock signal timings.